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Altera_Forum
Honored Contributor
15 years agoVHDL robot design not working
Hello everybody I'm new in VHDL and I'm doing a project with DE2 board In the project I need to build a robot. My first step was to design a ASM and from that to take out the FSM which i...
Altera_Forum
Honored Contributor
15 years agoadd a reset at the beginning of the process, like this:
begin
wait until rising_edge(Clk);
Enable <= '1';
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
and you'll get waves like this: