VHDL robot design not working

Hii again

the code has changed (add generic and a constant) and I am using the modelsim now insted of the active hdl

but I still don't see any waves in the simulation :mad:

 
 
library IEEE;
 use IEEE.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
Entity Pwm is
 generic (
    DC    : time:=1 ms;
    clock_period: time:=20 ns
  );
    Port (    Rst : In  std_logic;
              Clk : In  std_logic;
              Sw : In  std_logic_vector (2 downto 0);
              Enable : in std_logic;
              Led : buffer std_logic_vector (7 downto 0);
     Pwm : Out std_logic
     );
    
  attribute altera_chip_pin_lc: string;
  attribute altera_chip_pin_lc of Clk  : signal is "@N2";
  attribute altera_chip_pin_lc of Rst : signal is "@G26";
  attribute altera_chip_pin_lc of Led  : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21, @AC21";
  attribute altera_chip_pin_lc of Sw    : signal is "@N25,@N26, @P25";
  attribute altera_chip_pin_lc of Enable: signal is "@AE14";
  
end entity Pwm;
Architecture arc_Pwm of Pwm is
constant duty_cycle: integer:=DC/clock_period;
signal Counter : std_logic_vector (16 downto 0);
begin
PwmReg: process (Clk,Rst,Sw)
begin
  if (Rst='1') then
    Counter <= (others=>'0');
    Pwm <='0';
    Led <= (others=>'0');
  elsif rising_edge(Clk) then
 if (Enable='1') then
  if (Counter = duty_cycle) then
   Counter <= (others => '0');
   if (Sw(0) = '1') and (Sw(1) = '0') and (Sw(2) = '0') then 
    led <= led + 1;
   elsif (Sw(0) = '0') and (Sw(1) = '1') and (Sw(2) = '0') then   
    led <= led - 1;
   end if;
  else
        Counter <= Counter + 1;
     end if; 
   end if;  
   if (Counter < duty_cycle) then
   Pwm <= '1';
    else
  Pwm <= '0';
   end if;
   end if;
end process PwmReg;
end architecture arc_Pwm;

 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use std.textio.all;
--use ieee.std_logic_textio.all;
------------------------------------------------------------------------------
entity tb_pwm is
end entity tb_pwm;
------------------------------------------------------------------------------
architecture arc_tb_pwm of tb_pwm is
  signal Clk : std_logic             := '0';  -- 
  signal Rst : std_logic               := '0';  -- 
  signal Sw  : std_logic_vector  (2 downto 0):= "000";    -- 
  signal Enable : std_logic      := '0';  -- 
  signal Pwm : std_logic;                     -- 
  signal Led : std_logic_vector(7 downto 0);  -- 
begin
  
  test : entity work.pwm
    
    port map (
      Clk  => Clk,  
      Rst  => Rst,  
      Enable => Enable, 
      Sw  => Sw,  
      Pwm  => Pwm,  
      Led  => Led );                              
  Clk <= not Clk after 10 ns;
  process
    
  begin
    wait until rising_edge(Clk);
    --wait on switch push;
    Enable <= '1';
--   l1 : loop
      wait until rising_edge(clk);
      --wait for 1 ns;
   Sw(0) <= '1';
   Sw(1) <= '0';
   Sw(2) <= '0';
   wait for  0.025us;
   wait until rising_edge(clk); 
   Sw(0) <= '0';
   Sw(1) <= '1';
   Sw(2) <= '0';
   wait for  0.025us;
      wait until rising_edge(clk);
   Sw(0) <= '0';
   Sw(1) <= '0';
   Sw(2) <= '1';
   wait for  0.025us;
      wait until rising_edge(clk);
      Enable <= '0';
   wait for 0.025us;
      wait until rising_edge(clk);
      Rst <='0'; 
      wait for  0.025us;     
  end process;
end architecture arc_tb_pwm;

In the do file I wrote 1us and in the tb iwrote 0.025us in order to see it in the simulaton

thanks in advance