VHDL robot design not working

hi,

I changed the sw time to 50 ns even though I dont think its the problme,

because the simulation still needed to display the sw waves and I only see

clk wave and the others are : pwm - 'u' rst- 'x' others - '0'

but know the clock time << sw time , so that solve this issue.

I notice that I didnt included the generic map in the tb before so I did it now

from a VHDL examples folder and I hope I did it right.

but still there no changes in the waves ... so what now?:confused:

 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use std.textio.all;
--use ieee.std_logic_textio.all;
------------------------------------------------------------------------------
entity tb_pwm is
end entity tb_pwm;
------------------------------------------------------------------------------
architecture arc_tb_pwm of tb_pwm is
  signal Clk : std_logic             := '0';  -- 
  signal Rst : std_logic               := '0';  -- 
  signal Sw  : std_logic_vector  (2 downto 0):= "000";    -- 
  signal Enable : std_logic      := '0';  -- 
  signal Pwm : std_logic;                     -- 
  signal Led : std_logic_vector(7 downto 0);  -- 
begin
  
  test : entity work.pwm
    generic map(
                DC => 100 ns,
              clock_period => 20 ns
              )
a    port map (
                Clk  => Clk,  
                Rst  => Rst,  
                Enable => Enable, 
                Sw  => Sw,  
                Pwm  => Pwm,  
                Led  => Led );                              
  
  Clk <= not Clk after 10 ns;
  process
    
  begin
    wait until rising_edge(Clk);
    Enable <= '1';
    wait until rising_edge(clk);
   Sw(0) <= '1';
   Sw(1) <= '0';
   Sw(2) <= '0';
   wait for  100 ns;
   wait until rising_edge(clk); 
   Sw(0) <= '0';
   Sw(1) <= '1';
   Sw(2) <= '0';
   wait for  100 ns;
    wait until rising_edge(clk);
   Sw(0) <= '0';
   Sw(1) <= '0';
   Sw(2) <= '1';
   wait for 100 ns;
    wait until rising_edge(clk);
    Enable <= '0';
   wait for 100 ns;
    wait until rising_edge(clk);
    Rst <='0'; 
    wait for 100 ns;     
  end process;
end architecture arc_tb_pwm;