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Altera_Forum
Honored Contributor
Honored ContributorVHDL robot design not working
Hello everybody I'm new in VHDL and I'm doing a project with DE2 board In the project I need to build a robot. My first step was to design a ASM and from that to take out the FSM which i...
Altera_ForumHonored Contributor
Honored Contributorthe duty cycle is 50000, so you need at least this many clock cycles before LED is valid. Your entire simulation runs for 1 us at 100MHz, so you get a grand total of 100 clocks.
Another problem - you dont assert reset so your counter will never count (because it's all 'U' when it does try and count).
