Forum Discussion
Honored ContributorVHDL Package
Hi,
Pardon me if this is not the right place to post this question. Just a simple one. Im not too sure about this package thingy in vhdl coding. How does it differ from creating a component and how does it actually affect the performance in term of area and speed of the resulting implementation? thank you very much :)7 Replies
Altera_ForumThe package source can reside anywhere, but you have to include it in the project file list.
- Altera_Forum--- Quote Start --- Hi, I'm new using VHDL, I know how to create a package in Quartus II. I have had many problems doing that, when I use the package on another circuit, always sends me the following miss. Error (10482): VHDL error at SCnbitsPaquete.vhd(4): object "SCpaquete" is used but not declared I doubt where I have to save the package and if I have to paste the package into the folder on the new circuit. --- Quote End --- save a copy of the package file in the same folder with your current project
- Altera_Forum
Hi, I'm new using VHDL, I know how to create a package in Quartus II.
I have had many problems doing that, when I use the package on another circuit, always sends me the following miss. Error (10482): VHDL error at SCnbitsPaquete.vhd(4): object "SCpaquete" is used but not declared I doubt where I have to save the package and if I have to paste the package into the folder on the new circuit. - Altera_Forum
thanks alot! now I get the idea. :D
- Altera_Forum
You could create a package of arithmetic functions, but you'd still have to call the functions inside a process, or another function. A package on its own is not synthesizable. Only processes produce gates and registers. But if the arithmatic was complicated in some way it may make the code more readable, so you could write this in your entity:
you could create a component to do the arithmatic, but its no more or less benficial than just doing it in the same entity. Its down to personal preference and also whether it partitions the design into an easier to understand layout. At the end of the day, its the same gates and registers.process(clk) begin if rising_edge(clk) then output <= do_some_stuff(a, b); end if; end process; - Altera_Forum
say there is one particular part of the circuit require to perform certain arithmetic. it is more beneficial that i create component or package for it?
- Altera_Forum
A package and component are completly different things.
A component is a declaration of an entity, describing the ports and generics on the entity. Component declarations can exist inside a package so you dont have to keep copy/pasting them into every file that you want to instantiate the entity in. Since VHDL 93 component declarations are pretty well redundant as you can do the much more useful direct entity instantiations. The only time you need them is when you're instantiating entities from sources other than VHDL code (like AHDL, verilog, netlists etc) Packages are just a library of anything - constants, functions, procedures, components that you can then call into your VHDL entities. This means if you have some useful functions you want to use in several VHDL files, you contain it all inside a package.
