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Altera_Forum
Honored Contributor
Honored ContributorVHDL Package
Hi, Pardon me if this is not the right place to post this question. Just a simple one. Im not too sure about this package thingy in vhdl coding. How does it differ from creating a component and...
Altera_ForumHonored Contributor
Honored ContributorThe package source can reside anywhere, but you have to include it in the project file list.
