VHDL Package

A package and component are completly different things.

A component is a declaration of an entity, describing the ports and generics on the entity. Component declarations can exist inside a package so you dont have to keep copy/pasting them into every file that you want to instantiate the entity in. Since VHDL 93 component declarations are pretty well redundant as you can do the much more useful direct entity instantiations. The only time you need them is when you're instantiating entities from sources other than VHDL code (like AHDL, verilog, netlists etc)

Packages are just a library of anything - constants, functions, procedures, components that you can then call into your VHDL entities. This means if you have some useful functions you want to use in several VHDL files, you contain it all inside a package.