VHDL Package

You could create a package of arithmetic functions, but you'd still have to call the functions inside a process, or another function. A package on its own is not synthesizable. Only processes produce gates and registers. But if the arithmatic was complicated in some way it may make the code more readable, so you could write this in your entity:

process(clk) 
begin
  if rising_edge(clk) then
   output <= do_some_stuff(a, b);
  end if;
end process;

you could create a component to do the arithmatic, but its no more or less benficial than just doing it in the same entity. Its down to personal preference and also whether it partitions the design into an easier to understand layout. At the end of the day, its the same gates and registers.