vhdl coding

ya thanks for your quick response

actually i have taken if statements to insert the data into the register.

ex:

if (numofbits = "0011") then

data <= "111";

elsif(numofbits = "0100") then

data <= "1111";

end if;

so on i have to write code for variable numofbits for ex: 3 to 16 bits.

is there any other way of writing the code instead of using so many if and elsif statements.

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ya thanks for your quick response

actually i have taken if statements to insert the data into the register.

ex:

if (numofbits = "0011") then

data <= "111";

elsif(numofbits = "0100") then

data <= "1111";

end if;

so on i have to write code for variable numofbits for ex: 3 to 16 bits.

is there any other way of writing the code instead of using so many if and elsif statements.

--- Quote End ---

Just how does numofbits 'vary'? The way you've written the above, implies that it does not vary within a given design since if it did then the assignments to 'data' would not be correct since in one case data is three bits, the other it is four. I doubt that is what you intend, but if by chance it is then the code would be...

signal data: std_logic_vector(numofbits - 1 downto 0);

...

data <= (others => '1');

But like I said, I doubt that is what you intend. Instead, I'm guessing that numofbits is more variable than that, in which case the following would work...

signal data: std_logic_vector(??? downto 0); -- No idea how wide 'data' is

...

process

...

data <= (other => '0');

for i in 0 to (numofbits - 1) loop

data(i) <= '1';

end loop;

...

Kevin Jennings

the numofbits is an input to me it will vary from 3 to 16 bits so the length of my output register should depend on the numofbits not a fixed length. k i will try with the signal statements you have given.

thanks K_J

hi K_J

I have tried the signal statement

signal data: std_logic_vector(numofbits - 1 downto 0);

but i got an error that the numofbits does not support with its natural usage.

can you please help me.

ya i will explain you clearly............

data is an output and numofbits is an input for me . let suppose data is a fixed length of 8 bits. Then if numofbits is 4. I have to place 4 bits of data in the data register. The remaining bits will be zero. So, for avoiding that zeros in my data register the length of the data register should vary with respect to the numofbits

Data registers in FPGA are hardware elements that need to be assigned at compile time. There's nothing to avoid. The solution given by K_J is a reasonable answer to the problem. If the maximum number of bits is 16, 16 bits must be hold available, so you need to define

signal data: std_logic_vector(15 downto 0);

There's no other way in hardware logic design.