vhdl coding

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ya thanks for your quick response

actually i have taken if statements to insert the data into the register.

ex:

if (numofbits = "0011") then

data <= "111";

elsif(numofbits = "0100") then

data <= "1111";

end if;

so on i have to write code for variable numofbits for ex: 3 to 16 bits.

is there any other way of writing the code instead of using so many if and elsif statements.

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Just how does numofbits 'vary'? The way you've written the above, implies that it does not vary within a given design since if it did then the assignments to 'data' would not be correct since in one case data is three bits, the other it is four. I doubt that is what you intend, but if by chance it is then the code would be...

signal data: std_logic_vector(numofbits - 1 downto 0);

...

data <= (others => '1');

But like I said, I doubt that is what you intend. Instead, I'm guessing that numofbits is more variable than that, in which case the following would work...

signal data: std_logic_vector(??? downto 0); -- No idea how wide 'data' is

...

process

...

data <= (other => '0');

for i in 0 to (numofbits - 1) loop

data(i) <= '1';

end loop;

...

Kevin Jennings