Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

vhdl coding

hi am new to vhdl programming. I need help in wirting the code for inserting variable data into a register. the length of the register should be based on the number of bits of data am giving to the r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Data registers in FPGA are hardware elements that need to be assigned at compile time. There's nothing to avoid. The solution given by K_J is a reasonable answer to the problem. If the maximum number of bits is 16, 16 bits must be hold available, so you need to define 

signal data: std_logic_vector(15 downto 0);

There's no other way in hardware logic design.