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Honored Contributor
Honored ContributorVHDL Code
Hello Guys
I write this code with the max plus II. library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity axelaration_div is
port
(
in_divider : in integer range 0 to 2097151;
clk : in std_logic;
start : in std_logic;
out_divider : out integer range 0 to 2097151
);
end;
architecture arc_axelaration_div of axelaration_div is
signal div_num : integer range 0 to 65535 ;
signal cntr_01s : integer range 0 to 2400000;
signal cntr_ax : integer range 0 to 63;
signal flag_reset_div_num : std_logic;
signal flag_cntr_01s : std_logic;
begin
process (start)
begin
if rising_edge(start) then
if flag_reset_div_num ='1' then
div_num <= 5000;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
cntr_01s <= cntr_01s + 1;
end if;
end process;
process (clk)
begin
if falling_edge(clk) then
if flag_cntr_01s = '1' then
if cntr_01s = 2399999 then
cntr_01s <= 0;
cntr_ax <= cntr_ax + 1;
end if;
if cntr_ax = 3 then
cntr_ax <= 0;
div_num <= div_num - 1000;
end if;
if div_num = 2000 then
div_num <= in_divider;
end if;
end if;
--else
--out_divider <= div_num;
end if;
end process;
out_divider <= div_num;
end arc_axelaration_div;
I got an error message error: line 19: file c:\documents: unsupported feature error: unresolved signal is multiply driven What is this mean and how i can fix this Error? Thanks Amirster
