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Altera_Forum
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19 years ago

VHDL Code

Hello Guys I write this code with the max plus II. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity axelaration_div is ...
Altera_Forum's avatar
Altera_Forum
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19 years ago

You are driving the integer type signals "cntr_01s" and "div_num" from more than one process. The compiler can't determine which one of them that should set the signal value.

Integer is not a "resolved" type and cannot be driven by more than one driver.

Solve the problem by doing all assignments inside the same process.

Some signal types such as "std_logic" are resolved types. They will be evaluated if there are more than one driver process. Example driving an 'Z' and a '1' will resolve a '1' , driving a '1' and a '0' will resolve in an 'X'. This kind of usage is mostly used for test benches and simulation.

Different synthesizers and FPGA architecture handles resolved types differently too. Xilinx for example have FPGAs with tri-state buses internally, Altera doesn't.

/BitBuster