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Altera_Forum
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18 years ago

VHDL Code

Hello Guys I write this code with the max plus II. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity axelaration_div is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

There are still many errors. Input ports can't be used to drive signals(the 9th clause from the last, "div_num <= in_divider;" will be a VHDL syntax error).

I feel this code is very confused. I don't know what time sequece or logic are you want to realize. I think this is your homework, and you are a student.

You can send me an E-mail. I'd like to study it.