Honored ContributorHi!
This is my first post. I use Altera Quartus II and I have a question. It is possible to write a VHDL behavioral and use this VHDL code as "block" in schematic mode? It is possible interconnect many modules written in VHDL in graphics mode in schematic editor?
Honored ContributorYes. You can create a schematic from a VHDL file from the file menu. But be aware there are limits to the types you can use in the port definitiion.
Honored ContributorWhat is the procedure? And what are the limitations? I only use std_logic and std_logic_vector ...
Honored Contributor1. Open Project
2. Open VHDL source file 3. Under File -> Crate / Update -> Create Symbol Files for Current File I always use STD_LOGIC and STD_LOGIC_VECTOR.
