Forum Discussion
Altera_Forum
Honored Contributor
15 years ago1. Open Project
2. Open VHDL source file 3. Under File -> Crate / Update -> Create Symbol Files for Current File I always use STD_LOGIC and STD_LOGIC_VECTOR.1. Open Project
2. Open VHDL source file 3. Under File -> Crate / Update -> Create Symbol Files for Current File I always use STD_LOGIC and STD_LOGIC_VECTOR.