VHDL code for a sram

I see many problems with this code:

1. you're missing a few end if; lines

2. data_in <= temp; is not possible, because data_in is an input

3. you cant use [] in VHDL

I dont know what you're trying to do with the temp signal. You dont need it.

Fix these problems first, but you're nearly there.

Hi,

I have fixed those problems, my code looks like that now:

library ieee;

library work;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.all;

entity sram2 is

port (clk : in std_logic;

ce : in std_logic;

oe : in std_logic;

we : in std_logic;

LB : in std_logic;

UB : in std_logic;

addr : in std_logic_vector(17 downto 0);

data_in : inout std_logic_vector(15 downto 0);

data_out : out std_logic_vector(15 downto 0)

);

end sram2;

architecture syn of sram2 is

type ram_type is array (262144 downto 0) of std_logic_vector (15 downto 0);

signal RAM: ram_type;

signal temp: STD_LOGIC_VECTOR (15 downto 0);

begin

process (clk)

begin

if clk'event and clk = '1' then

if ce='1' then

RAM(conv_integer(addr)) <= "ZZZZZZZZZZZZZZZZ";

elsif ce = '0' then

if oe = '1' and we='1' then

report "Mauvaise valeur des signaux" severity warning;

elsif we='0' then

if UB='1' and LB='0' then

temp <= "ZZZZZZZZ"&data_in(7)&data_in(6)&data_in(5)&data_in(4)&data_in(3)&data_in(2)&data_in(1)&data_in(0);

data_in <= temp;

RAM(conv_integer(addr)) <= data_in;

elsif UB='0' and LB='1' then

temp <= data_in(15)&data_in(14)&data_in(13)&data_in(12)&data_in(11)&data_in(10)&data_in(9)&data_in(8)&"ZZZZZZZZ";

data_in <= temp;

RAM(conv_integer(addr)) <= data_in;

elsif UB='0' and LB='0' then

RAM(conv_integer(addr)) <= data_in;

end if;

elsif oe='0' then

if we='0' then

report "Mauvaise valeur des signaux" severity warning;

elsif we='1'then

if UB='1' and LB='0' then

RAM(conv_integer(addr))(15)<='Z';

RAM(conv_integer(addr))(14)<='Z';

RAM(conv_integer(addr))(13)<='Z';

RAM(conv_integer(addr))(12)<='Z';

RAM(conv_integer(addr))(11)<='Z';

RAM(conv_integer(addr))(10)<='Z';

RAM(conv_integer(addr))(9) <='Z';

RAM(conv_integer(addr))(8) <='Z';

data_out <= RAM(conv_integer(addr)) ;

elsif UB='0' and LB='1' then

RAM(conv_integer(addr))(7)<='Z';

RAM(conv_integer(addr))(6)<='Z';

RAM(conv_integer(addr))(5)<='Z';

RAM(conv_integer(addr))(4)<='Z';

RAM(conv_integer(addr))(3)<='Z';

RAM(conv_integer(addr))(2)<='Z';

RAM(conv_integer(addr))(1)<='Z';

RAM(conv_integer(addr))(0)<='Z';

data_out <= RAM(conv_integer(addr)) ;

else

data_out <= RAM(conv_integer(addr)) ;

end if;

end if;

end if;

end if;

end if;

end process;

end syn;

My question is that ModelSim does not recognized 'Z' which is high-Z. How can I do?

thanks for your answer

assuming all signals are active low:

elsif we='0' then
  if UB='1' and LB='0' then
    temp <= "ZZZZZZZZ"&data_in(7)&data_in(6)&data_in(5)&data_in(4)&data_in(3)&data_in(2)&data_in(1)&data_in(0);
    data_in <= temp;
    RAM(conv_integer(addr)) <= data_in;

you cant do this. You will be driving against data in. But temp is also a signal, so you're messing around with registers all over that you dont want.

all you need is:

if UB='1' and LB='0' then
  RAM(conv_integer(addr))(7 downto 0) <= data_in(7 downto 0);
elsif UB='0' and LB='1' then
  RAM(conv_integer(addr))(15 downto 7) <= data_in(15 downto 7);
end if;

also - you dont need to set individual bits to 'z' - you can do whole ranges:

data_in <= (others => 'z');

basically - delete the temp signal completly - its confusing you and not doing anything for you. You also should declare data_in as an in, not an inout (otherwise it needs renaming). And if this is internal ram, you cant have inouts anyway - you can only have inouts connected to FPGA pins.

Now, I think you can work the rest out.

Thank you for your help; i have just another question. I am working with a 512 kB SRAM with 144 words x 16 bits. In the array of my ram_type what should I put?

thanks

Elea

i have also another request. I am looking for the VHDL code of the SRAm controller SLS_UP3_SRAM. In fact, the SRAM controller provided by altera in SOPC Builder for the cyclone II development board seems not usable to me because it is made for a stratix development board which sram has a 32 width data bus (there is written when I generate my system : data_to_and_from_the_de1_sram). So i read somewher ethat the sram controller I need is SLS_UP3_SRAM but I do not find it!

Can someone help me pleaase?

i had another solution which was to take a _hw.tlc file and to edit a new component with it but I do not know how to do it with SOPC Builder. It seems that it does not work properly when I do it.:mad: