VHDL code for a sram

assuming all signals are active low:

elsif we='0' then
  if UB='1' and LB='0' then
    temp <= "ZZZZZZZZ"&data_in(7)&data_in(6)&data_in(5)&data_in(4)&data_in(3)&data_in(2)&data_in(1)&data_in(0);
    data_in <= temp;
    RAM(conv_integer(addr)) <= data_in;

you cant do this. You will be driving against data in. But temp is also a signal, so you're messing around with registers all over that you dont want.

all you need is:

if UB='1' and LB='0' then
  RAM(conv_integer(addr))(7 downto 0) <= data_in(7 downto 0);
elsif UB='0' and LB='1' then
  RAM(conv_integer(addr))(15 downto 7) <= data_in(15 downto 7);
end if;

also - you dont need to set individual bits to 'z' - you can do whole ranges:

data_in <= (others => 'z');

basically - delete the temp signal completly - its confusing you and not doing anything for you. You also should declare data_in as an in, not an inout (otherwise it needs renaming). And if this is internal ram, you cant have inouts anyway - you can only have inouts connected to FPGA pins.

Now, I think you can work the rest out.