VHDL architecture

Well, VHDL isn't the best for you task. In Verilog you can simply copy-past piece of code into different file and add `include directive inplace. VHDL hasn't got preprocessing suport.

BTY, as I see you have to understand HDL coding in common. There is no difference in which file process is implemented, the main distinct is a module. In VHDL you can move calibration process into the new module (and new file) and instantiate it at the high-level.

I think VHDL will do fine for what you want Dvido. I'm just a bit unsure of the details. If you post some code then it might help.

There are various ways of doing what you want. Probably I would suggest instantiating your calibration code and project code side by side in a new top level. Use the calibration code to hold the project code in reset until it completes.

If the entity is the same for project and calibration then you can just have a different architecture for each (entities and architectures don't have to be in the same file).

If you use direct instantiation then you don't need to declare the component and you can specify the architecture for each instance:

project_instance : entity work.dvido_entity(project)
port map (
);
calibration_instance : entity work.dvido_entity(calibration)
port map (
);

Hope this helps

batfink

Hi batfink,

Thanks for the reply, it is very helpful. Let me explain exactly what I need to do and maybe you can tell me which is the best way to do it.

I have a working code (with a working circuit) that functions fine.

My circuit have to be self-calibrated. The self calibration should happen once, after the first power-up. I also need an option to perform the self-calibration again once in a while but basically it should happen once.

What I need to do is to run the self-calibration and once it is finished to run the working code that I have right now. The calibration process will use some of the pins that are used by the proper code.

What will be the difference between implementing these 2 tasks (self-calibration and proper code) in 2 different entities or 2 different architectures in the same entity?

Also, can you explain a little more about multiple architectures for the same entity?

Thanks,

Dvido

Dvido

I think that you need to think about your design functionality a bit and whether your calibration is in fact part of your main design. Without knowing your project it's difficult to suggest anything but bear in mind that you are designing a logic circuit - not software code. Your code is synthesised and the synthesised logic exists throughout the life of power on the chip - i.e. code doesn't run and then disappear - the logic is always there regardless of whether it is doing anything useful at any particular time.

If you create a whole lump of logic to do some calibration straight after power up and then disable this and enable another lump of logic, both lumps of logic exist at all times - you're just freezing one of them at a time.

Sketch out a block diagram of what you're design is doing if you're getting stuck - this approach usually helps you get things straight in your head.

As far as two architectures for the same entity go you it's fairly self explanatory - you just write two architectures:

entity my_entity is
port ( A : in std_logic;
         B : in std_logic;
         Q : out std_logic
    );
architecture rtl of my_entity is
Q <= A and B;
end rtl;
architecture behave of my_entity is
Q <= A and B after 10 ns;
end behave;

The architectures and entity can be in the same or different files but bear in mind that the entity has to be compiled first - I would suggest either putting them all in the same file or all in their own fine (i.e. don't put the entity and one architecture in one file and the second architecture in a different file; don't duplicate the entity).

You can specify which architecture you instantiate either as I showed you previously or using configurations. If you don't specify the architecture then the most recently compiled one will be used.

From what you've said though I think that you need to think about the structure of your project a little bit.