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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL architecture

Hi, I am pretty new to VHDL, I've only wrote relatively small projects. I am looking for a good explanation on how to design a big VHDL project with multiple files, entities, functions etc. For ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Well, VHDL isn't the best for you task. In Verilog you can simply copy-past piece of code into different file and add `include directive inplace. VHDL hasn't got preprocessing suport.

BTY, as I see you have to understand HDL coding in common. There is no difference in which file process is implemented, the main distinct is a module. In VHDL you can move calibration process into the new module (and new file) and instantiate it at the high-level.