VHDL architecture

I think VHDL will do fine for what you want Dvido. I'm just a bit unsure of the details. If you post some code then it might help.

There are various ways of doing what you want. Probably I would suggest instantiating your calibration code and project code side by side in a new top level. Use the calibration code to hold the project code in reset until it completes.

If the entity is the same for project and calibration then you can just have a different architecture for each (entities and architectures don't have to be in the same file).

If you use direct instantiation then you don't need to declare the component and you can specify the architecture for each instance:

project_instance : entity work.dvido_entity(project)
port map (
);
calibration_instance : entity work.dvido_entity(calibration)
port map (
);

Hope this helps

batfink