New ContributorVHDL-2008: When defining an entity I want to use unconstrained types as ports. Do I have to give the dimensions of these ports as generics or can I define the entity fully unconstrained?
According to VHDL-2008, unconstrained types are allowed, but signals must be constrained when they are declared.
That leaves the above question open: One can imagine the following:
entity unconstrained_dummy is
port (
clk : in std_logic;
signal_i : in std_logic_vector;
signal_o: out std_logic_vector
);
end unconstrained_dummy;
architecture rtl of unconstrained_dummy is
negate: for i in signal_i'range generate
begin
signal_o(i) <=not signal_i(i);
end generate;
end rtl;
And then instantiating this entity in another one, where a signal is defined that constraines its size:
...
signal fancy_signal: std_logic_vector(7 downto 0);
signal fancy_out_signal: std_logic_vector(7 downto 0);
begin
...
negate_inst: entity work.unconstrained_dummy
port map (
signal_i => fancy_signal,
signal_o => fancy_out_signal
);
...
This seems to work when remaining in one library, but when I try using "unconstrained_dummy" from a different library (via a sub-entity), it seems to collapse the bit width of signal_i and signal_o to 0 downto 0.
The solution is clearly to define the actual bit width as a generic, but that's cumbersome. Do I overinterpret the "new" VHDL-2008 feature of unconstrained arrays?
Or is the way to go to pass the signal type in the generics (which seems to result in the same) ...?
Please bring light into darkness and indicate where the restrictions/limitations are and how this is supposed to be done properly for entities.
Thanks and tschö, Steffen
