VHDL-2008: When defining an entity I want to use unconstrained types as ports. Do I have to give the dimensions of these ports as generics or can I define the entity fully unconstrained?

Hi Steffan,

Sorry for the late response. In VHDL 2008, the actual width of an unconstrained component port can be set by connecting a constrained signal in the instantiation, you would not even need generics for it. You can check on your side. It is discussed as an example based on cases for composite subtype -> interface object in a link I will email to you.

For example unconstrained port:

entity ent2 is port ( p : out std_logic_vector );

end entity ent2;

we might write an instance as follows:

signal s12 : std_logic_vector(15 downto 4); ...

inst4 : entity work.ent2(a) port map ( p => s12 );

In this example, the index range of the formal is not defined, and the association with the actual provides no index values to use. So the formal takes its index range, 15 down to 4, from the associated actual signal s12. There few subcases dicussed in the link I email to you for like variable and signal delcaration, constant declaration etc

And the VHDL-2008 compilation and synthesis tool also depend on the version of Quartus Prime support for the language. Refer to link below for details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf

Thanks,

Regards