Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL -> Verilog for loop conversion
I have been attempting to convert some code I have written from VHDL to Verilog without much success. My main stumbling block is the for loops in my VHDL code. My FOR loops have a much larger index, I am using 0 to 1 for simplicity.
Simplified VHDL example:PROCESS(CLK)
BEGIN
IF (rising_edge(CLK)) THEN
FOR I IN 0 TO 1 LOOP
data_s(((8*I)+7) DOWNTO (8*I)) <= data_s(((8*I)+7) DOWNTO (8*I)) + '1';
END LOOP;
END IF;
END PROCESS;PROCESS(CLK)
BEGIN
IF (rising_edge(CLK)) THEN
data_s(7 DOWNTO 0) <= data_s(7 DOWNTO 0) + '1'
data_s(15 DOWNTO 8) <= data_s(15 DOWNTO 8) + '1'
END IF;
END PROCESS;always @(*) begin : data_increment_loop_I
integer i;
for(i=0;i<1;i=i+1) begin : Loop_lane_increment_i
data_plus_1_s = data_s + 1;
end
end
always @ (posedge CLK) begin
data_s <= data_plus_1_s;
end2 Replies
Altera_ForumFirst comment, for(i=0;i<1;i=i+1) is evaluating the following code only once (for i = 0), not the same thing that the VHDL equivalent does.
Secondly, the "range" select problem can be solved in Verilog by a construct called indexed part select, see an example from Std IEEE 1364, particularly the last line:
The basic solution working without "advanced" Verilog syntax, that's possibly missing from a "Verilog for beginners" tutorial, is using nested loops. Although VHDL to Verilog translation by trial-and-error method will work somehow, it's possibly less frustrating with a profound Verilog text book at hand.reg big_vect; reg little_vect; reg dword; integer sel; big_vect // == big_vect big_vect // == big_vect little_vect // == little_vect little_vect // == little_vect dword // variable part-select with fixed width- Altera_Forum
Thanks for the reply. I agree, my verilog for loop only evaluates for i=0. I should have caught that for the example.
"indexed part select" is exactly what I needed. Thanks for the help.
