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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL -> Verilog for loop conversion

I have been attempting to convert some code I have written from VHDL to Verilog without much success. My main stumbling block is the for loops in my VHDL code. My FOR loops have a much larger index, I am using 0 to 1 for simplicity.

Simplified VHDL example: 

PROCESS(CLK)
BEGIN
    IF (rising_edge(CLK)) THEN
        FOR I IN 0 TO 1 LOOP
            data_s(((8*I)+7) DOWNTO (8*I)) <= data_s(((8*I)+7) DOWNTO (8*I)) + '1';
        END LOOP;
    END IF;
END PROCESS;

When this is simplified by the compiler (during analysis and synthesis), it looks like this: 

PROCESS(CLK)
BEGIN
    IF (rising_edge(CLK)) THEN
        data_s(7 DOWNTO 0) <= data_s(7 DOWNTO 0) + '1'
        data_s(15 DOWNTO 8) <= data_s(15 DOWNTO 8) + '1'
    END IF;
END PROCESS;

I have ended up generating code that I think is close, but still has issues: 

always @(*) begin : data_increment_loop_I
    integer i;
    for(i=0;i<1;i=i+1) begin : Loop_lane_increment_i
        data_plus_1_s = data_s + 1;
    end
end
always @ (posedge CLK) begin
    data_s <= data_plus_1_s;
end

I end up with "Range must be bounded by constant expressions." on data_plus_1_s and data_s.

Suggestions on better ways to code this (other than write them all out individually) would be most appreciated.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    First comment, for(i=0;i<1;i=i+1) is evaluating the following code only once (for i = 0), not the same thing that the VHDL equivalent does.

    Secondly, the "range" select problem can be solved in Verilog by a construct called indexed part select, see an example from Std IEEE 1364, particularly the last line: 

    reg  big_vect;
reg  little_vect;
reg  dword;
integer sel;
big_vect // == big_vect
big_vect // == big_vect
little_vect // == little_vect
little_vect // == little_vect
dword // variable part-select with fixed width

    The basic solution working without "advanced" Verilog syntax, that's possibly missing from a "Verilog for beginners" tutorial, is using nested loops.

    Although VHDL to Verilog translation by trial-and-error method will work somehow, it's possibly less frustrating with a profound Verilog text book at hand.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks for the reply. I agree, my verilog for loop only evaluates for i=0. I should have caught that for the example.

    "indexed part select" is exactly what I needed. Thanks for the help.