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Altera_Forum
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13 years ago

VHDL -> Verilog for loop conversion

I have been attempting to convert some code I have written from VHDL to Verilog without much success. My main stumbling block is the for loops in my VHDL code. My FOR loops have a much larger index...
Altera_Forum's avatar
Altera_Forum
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13 years ago

First comment, for(i=0;i<1;i=i+1) is evaluating the following code only once (for i = 0), not the same thing that the VHDL equivalent does.

Secondly, the "range" select problem can be solved in Verilog by a construct called indexed part select, see an example from Std IEEE 1364, particularly the last line: 

reg  big_vect;
reg  little_vect;
reg  dword;
integer sel;
big_vect // == big_vect
big_vect // == big_vect
little_vect // == little_vect
little_vect // == little_vect
dword // variable part-select with fixed width

The basic solution working without "advanced" Verilog syntax, that's possibly missing from a "Verilog for beginners" tutorial, is using nested loops.

Although VHDL to Verilog translation by trial-and-error method will work somehow, it's possibly less frustrating with a profound Verilog text book at hand.