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Altera_Forum
Honored Contributor
Honored ContributorVHDL -> Verilog for loop conversion
I have been attempting to convert some code I have written from VHDL to Verilog without much success. My main stumbling block is the for loops in my VHDL code. My FOR loops have a much larger index...
Altera_ForumHonored Contributor
Honored ContributorThanks for the reply. I agree, my verilog for loop only evaluates for i=0. I should have caught that for the example.
"indexed part select" is exactly what I needed. Thanks for the help.
