Version upgrade (how to debug)

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We have been working on a design with Quartus v6.0 for quite some time. Synthesis result, simulation result, and actually on-device testing are working properly. But since we have switched to Quartus 8.1 (and even later v9.0), we can encounter unexpected results on some testcases. After a long investigation, it turns out to be Quartus version related.

In order to nail down the issue, we have used different versions for different design phase, and we believe the issue is related to the synthesis phase. [We have used the older v6.0 to synthesis the design, wrote out the vqm and use v8.1 for fitter, and it works fine]

We would like to know if there is any specific update going from v6.0 to v8.1 which we should have been aware of. Otherwise, can anyone provide some suggestion on how to debug this synthesis related issue? as it is very difficult to debug with the output vqm. (note that, the newer versions work for some testcases but not all)

Any insight/suggestion would be highly appreciated.

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Hi,

first of all can you explain a little bit more about your problem. Is it a timing issue or a

real logical misfunction ?. Have a look to the warnings of the different version. Any additional one ?

Kind regards

GPK

Hi,

I think I may have seen this before. I noticed that the default synth options changed between the releases, which for some devices can give different synth results.

I would reccommend visually comparing the synthysis advanced options for your 6.X and 8.X projects. Are you seeing functional differences, or resource differencs or both, also whats the device?

Dear GPK and Quartus Penguin,

Thanks for your response,

the problem is testcase/design dependence. In some cases, the state machine is stuck in an unknown state, and we were not able to reproduce the problem in simulation.

May i know the "resource differences" is reffering to?

How can I verify (generate report) of all synthesis options?

Is there a way to save warning/error reports in txt file?

We are using Quartus v6.0, v8.1 and v9.0.

Best regards

Jenny

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Dear GPK and Quartus Penguin,

Thanks for your response,

the problem is testcase/design dependence. In some cases, the state machine is stuck in an unknown state, and we were not able to reproduce the problem in simulation.

May i know the "resource differences" is reffering to?

How can I verify (generate report) of all synthesis options?

Is there a way to save warning/error reports in txt file?

We are using Quartus v6.0, v8.1 and v9.0.

Best regards

Jenny

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Hi,

sometimes it looks like that the synthesis tools are the reaason of the problem, but later it turns out that the design description is the root cause e.g. not all states of a state machine are covered, no reset for a statemachine , reset signals are not synchronized to the clock domain. I could imagine that the different versions of Quartus will deliver different results in such cases. Maybe it is a good idea to ahve a look into your design.

Kind regards

GPK