Verilog to VHDL

Hi everyone,

I am having a problem converting a verilog code to vhdl. I know there is a tool does that but it is not working properly. I did write the code in vhdl and the schematic is same. however the output of the two designs are completely different. I have a doubt about the accumulator, could anyone help me figure out what i am doing wrong here.

`timescale 100 ps / 10 ps
`define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac(DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input  DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg  DeltaAdder; // Output of Delta adder
reg  SigmaAdder; // Output of Sigma adder
reg  SigmaLatch; // Latches output of Sigma adder
reg  DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch, SigmaLatch} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <=# 1 1'b1 << (`MSBI+1);
DACout <=# 1 1'b0;
end
else
begin
SigmaLatch <=# 1 SigmaAdder;
DACout <=# 1 SigmaLatch;
end
end
endmodule

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
　
entity dac_vhdl is
                port(clk,reset : in std_logic;
                     DAC_in : in std_logic_vector(7 downto 0);
                     DAC_out : out std_logic);
end entity;
architecture beh of dac_vhdl is
signal Adder1_out : std_logic_vector(9 downto 0):=(others=>'0');
signal Adder2_out : std_logic_vector(9 downto 0):=(others=>'0');
signal Latch_out_sig : std_logic_vector(9 downto 0):=(others=>'0');
signal adder1_in : std_logic_vector(9 downto 0):=(others =>'0');
signal Latch_out : std_logic;
　
begin
Latch_out<= Latch_out_sig(9);
process (Latch_out)
begin
Adder1_in(9 downto 0) <= Latch_out_sig(9)&Latch_out_sig(9)& "00000000";
end process;
process(DAC_in, Adder1_in)
begin
Adder1_out(9 downto 0) <= DAC_in(7 downto 0) + Adder1_in(9 downto 0) ;
end process;
process(Latch_out, Adder1_out)
begin
Adder2_out(9 downto 0) <= Adder1_out(9 downto 0) +  Latch_out_sig(9 downto 0) ;
end process;
process(clk,Reset)
begin
if(Reset='1')then
Latch_out_sig<= "1000000000";
elsif(clk'event and clk='1')then
Latch_out_sig(9 downto 0) <= Adder2_out(9 downto 0);
end if;
end process;
&#12288;
process(clk,Reset)
begin
if(Reset='1')then
DAC_out<='0';
elsif(clk'event and clk='1')then
DAC_out <= Latch_out;
end if;
end process;
end beh;