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Altera_Forum
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13 years ago

Verilog to VHDL

Hi everyone, I am having a problem converting a verilog code to vhdl. I know there is a tool does that but it is not working properly. I did write the code in vhdl and the schematic is same. howev...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Both designs are identical, except for one detail. The SigmaLatch initializers have different bit patterns. If you correct the VHDL code respectively, both synthesize to the same gate level code. 

SigmaLatch <=# 1 1'b1 << (`MSBI+1);

Sets this bit pattern: 

Latch_out_sig<= "0100000000";

If you are referring to X-HDL, it's performing good I think, but needs either well considered rules or some manual rework.