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Altera_Forum's avatar
Altera_Forum
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13 years ago

Verilog to VHDL

Hi everyone, I am having a problem converting a verilog code to vhdl. I know there is a tool does that but it is not working properly. I did write the code in vhdl and the schematic is same. howev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

It's a pure simulation issue.

I was only talking about synthesis results and didn't check your code regarding simulation consistency, but I notice that you have wrong sensitivity list entries. Quartus warns about it.