Forum Discussion
Honored ContributorVCCIO Voltage Change
Hi,
I use EP3C10F256C8 chip , VCCIO set 1.8V , if other IO pin input set Hi(3.3V), result VCCIO change 2.2V? VCCIO set 1.5V , if other IO pin input set Hi(3.3V), result VCCIO change 2.2V?14 Replies
Altera_ForumThank you for mentioning AN447. It's scope is different however, targetting to the said overshoot problem. So it effectively doesn't give new insights why the original Multi-IO feature has been abandoned I think.
- Altera_Forum--- Quote Start --- I would ask support, if they can tell what exactly happens in this situation and if there's a risk of either device damage or temporary functional failure. I fear, you don't get a satisfying answer. Frank --- Quote End --- I filed a service request and the answer was only partly satisfying. There is a kind of multivoltage I/O application note for Cyclone III and IV. It is AN447 (http://www.altera.com/literature/an/an447.pdf) (http://www.altera.com/literature/an/an447.pdf%29). This application note however is limited to 2.5V, 3.0V and 3.3V I/O. Although I try to push him a bit, the application engineer advices to keep the input voltage below te recommended Vih,max. An overshoot voltage of 3.95V can be applied for 100% of the time over a 10 year period. I don't get any statement about what happens when I drive the input with a voltage between Vih,max and Vovershoot. Regards, Ton
- Altera_Forum
I would ask support, if they can tell what exactly happens in this situation and if there's a risk of either device damage or temporary functional failure. I fear, you don't get a satisfying answer.
At days of MultiVolt I/O Interface specification, there has been a comment about possible increased leakage currents when overdriving inputs. As one explanation, leakage currents may have increased above reasonable bounds with newer chip technologies. The other point is, that since Cyclone III publications are accompanied by permanent "watch your step" directions related to 3.3V operation, as if the authors can't imagine that a designer would be ever able to manage overshoots and keep the maximum voltage ratings. Forbidding input overdrive may be another means to save the chip in this view. Frank - Altera_Forum--- Quote Start --- Furthermore, a similar specification of a Vih,max value can't be found with any other logic device, I think. Personally, I won't take the specification too seriously, but don't suggest to ignore it, of course. --- Quote End --- I checked the Cyclone III, Cyclone IV and Stratix IV specifications, which I all used recently, and they all define Vih,max. They also define an overshoot voltage of 3.95 or 4V, for 100% of the time. I'm willing not to take these specification too seriously, but I also don't want to take too much risk, so I still wonder if someone knows the answers to the previously asked questions: --- Quote Start --- So in the most worst-case situation at VCCIO of 1.2V, can I set my input to 3.95V for 100% of the time without damaging my component? May I pull-up the opendrain CONF_DONE to 3.95V if VCCIO is 1.2V? --- Quote End --- Thanks, Ton
- Altera_Forum
Yes you're right. Altera cancelled the "MultiVolt I/O Interface" that has been featured until Cyclone II, MAX II and Stratix II, without any explanation or understandable reason as far as I'm aware of. Furthermore, a similar specification of a Vih,max value can't be found with any other logic device, I think. Personally, I won't take the specification too seriously, but don't suggest to ignore it, of course.
Thanks for the clarifcation. - Altera_Forum
My version from januari 2010 shows both VIH,min and VIH, max.
Here it is. Regards, Ton - Altera_Forum
If you refer to the same table 1-13, I find in the hardware manual (Cyclone III Devices Single-Ended I/O Standard Specifications), it's showing Vih min values. So it doesn't say anything about allowed maximum input levels.
- Altera_Forum
I checked the Multi-IO paragraph of C3 and some details drawed my attention:
* VIH,max for all I/O standards (except 1.8V) is VCCIO + 0.3V and VIL,min for most of the I/O standards is -0.3V (table1-13). This could suggest the use of schottky clamping diodes. But that's not the case, as already mentioned. * VI is recommended from -0.5V to 3.6V (table 1-3). No VCCIO mentioned in this table, so I assume for every possible VCCIO. * A VI,overshoot of 3.95V is allowed for 100% of the time (table 1-2). Also here no VCCIO mentioned in this table, so I assume for every possible VCCIO. So in the most worst-case situation at VCCIO of 1.2V, can I set my input to 3.95V for 100% of the time without damaging my component? May I pull-up the opendrain CONF_DONE to 3.95V if VCCIO is 1.2V? Just curious, -- Ton A related thread: http://www.alteraforum.com/forum/showthread.php?p=26563 - Altera_Forum
You are right to mention the programmable PCI clamp diodes, but these are the only positive clamping diodes in Altera FPGA. The lack of hardwired clamp diodes is implicitely clear from the "Multi-IO" paragraphs in various hardware manuals. Also maximum ratings would look different otherwise.
Frank - Altera_Forum
Thanks fo clarifying this. I thought the use of substate diodes was common practise to protect the silicon. On the other hand, it does have some disadvantages.
I always wondered if Altera used substrate diodes. This was never mentioned explicitly in the documentation I've read. But because you can switch on and off PCI clamping diodes, I doubted about this. Now I know. Thanks. Regards, Ton
