Honored ContributorHi,
I use EP3C10F256C8 chip , VCCIO set 1.8V , if other IO pin input set Hi(3.3V), result VCCIO change 2.2V? VCCIO set 1.5V , if other IO pin input set Hi(3.3V), result VCCIO change 2.2V?
Honored ContributorYou should not set your input to 3.3V if VCCIO is 1.5V or 1.8V. There's a big chance you will damage your device. Your VCCIO will settle somewhere between 3.3V and 1.5V, depending on the output impedances of your sources and the diode junctions in the path.
If your source is 3.3V, use 3.3V VCCIO or a level translator or a voltage divider. Success, TonHonored ContributorSo, VCCIO6 set 1.8V , CONF_DONE pin not > 1.8V ?
Honored ContributorHi Leo,
It is not aways easy to express yourself in a foreign language. I'm not a native english speaker and neither are you, I assume. Your post is too cryptic for me. Could you please use some more words to clarify your question? Maybe then I, or other members of this forum, could be of help. Anyway, I'll give it a shot: CONF_DONE is an open-drain output. If use a pull-up to 1.8V, the voltage on this pin will remain below 1.8V. If you use a pull-up to 3.3V, the voltage will rise above 1.8V, probably Vf,diode. I would not recommend this. It could damage your FPGA. -- TonHonored ContributorI also couldn't clearly understand the question, but some above told assumptions are wrong. Particularly, Altera FPGAs don't have substrate diodes between I/O pins and any supply voltage. So it's always safe to overdrive an I/O pin with a higher logic voltage, of course paying attention to the maximum ratings. The input thresholds are expected to change with VCCIO, however.
Honored ContributorThanks fo clarifying this. I thought the use of substate diodes was common practise to protect the silicon. On the other hand, it does have some disadvantages.
I always wondered if Altera used substrate diodes. This was never mentioned explicitly in the documentation I've read. But because you can switch on and off PCI clamping diodes, I doubted about this. Now I know. Thanks. Regards, TonHonored ContributorYou are right to mention the programmable PCI clamp diodes, but these are the only positive clamping diodes in Altera FPGA. The lack of hardwired clamp diodes is implicitely clear from the "Multi-IO" paragraphs in various hardware manuals. Also maximum ratings would look different otherwise.
FrankHonored ContributorI checked the Multi-IO paragraph of C3 and some details drawed my attention:
* VIH,max for all I/O standards (except 1.8V) is VCCIO + 0.3V and VIL,min for most of the I/O standards is -0.3V (table1-13). This could suggest the use of schottky clamping diodes. But that's not the case, as already mentioned. * VI is recommended from -0.5V to 3.6V (table 1-3). No VCCIO mentioned in this table, so I assume for every possible VCCIO. * A VI,overshoot of 3.95V is allowed for 100% of the time (table 1-2). Also here no VCCIO mentioned in this table, so I assume for every possible VCCIO. So in the most worst-case situation at VCCIO of 1.2V, can I set my input to 3.95V for 100% of the time without damaging my component? May I pull-up the opendrain CONF_DONE to 3.95V if VCCIO is 1.2V? Just curious, -- Ton A related thread: http://www.alteraforum.com/forum/showthread.php?p=26563Honored ContributorIf you refer to the same table 1-13, I find in the hardware manual (Cyclone III Devices Single-Ended I/O Standard Specifications), it's showing Vih min values. So it doesn't say anything about allowed maximum input levels.
Honored ContributorMy version from januari 2010 shows both VIH,min and VIH, max.
Here it is. Regards, TonHonored ContributorYes you're right. Altera cancelled the "MultiVolt I/O Interface" that has been featured until Cyclone II, MAX II and Stratix II, without any explanation or understandable reason as far as I'm aware of. Furthermore, a similar specification of a Vih,max value can't be found with any other logic device, I think. Personally, I won't take the specification too seriously, but don't suggest to ignore it, of course.
Thanks for the clarifcation.
