New ContributorHI,
I am using Quartus pro 21.2
1) Generate Simulation model for VCS
2) go to generate folder
( Audio.v : my generated PLL name )
3) This is user Guide for quartus prime pro
4) In server.
soruce genetated.tcl Not working.
5) Guide and script content not same
this is generated file.
this is guide.
--> How to RTL simulation from quatus pro geneated IP?
Just edited script not help.
I need help.
Super ContributorHi @minjoolee
Have you Generate the Simulator Setup Script in the document section 2.5.3.2.1. ?
Intel Quartus Prime Pro Edition User Guide: Third-party Simulation
Tools > Generate Simulator Setup Script for IP
The script should be in vcs_setup.sh or vcsmx_setup.sh files generated in your project directory.
Please go through Section 2 Intel FPGA Simulation Basics first to understand the simulation flow before go to section 4.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
New ContributorHI , this is my answer
Have you Generate the Simulator Setup Script in the document section 2.5.3.2.1. ?
--> YES
SEE second screen shots
1) scripts result are not same as
Intel Quartus Prime Pro Edition User Guide: Third-party Simulation
2) Without ignore comments in script,
cmd> source vcs_setup.sh
should be working. but not.
3) Can I get simple example such as only 1 PLL design for VCS RTL simulation .
to see waveform ( generated FSDB )
Thanks
Super ContributorThe screenshot resolution is bad to look at but the second screenshot seems to generate HDL for the specific IP. Does not look like it generate the Simulator Setup Script.
Anyhow, you may checkout the User Guide below on how to run the simulation using the Questa Intel FPGA Edition. The scripting concept is the same for VCS.
https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html
