Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Using LVDS Rd, StratixIII 1v8 VCCIO

I get an error message when trying to apply a differential OCT (Rd) to an LVDS clock input which is on a bank with VCCIO=1v8 in a SIII part:

Error: I/O bank 1C contains I/O pin p_rclk3 with Termination logic option setting Differential, so the I/O bank's VCCIO must be set to 2.5V

We are using the CLK0 pins which do support Rd. After much reading, I can't see why I'm supposed to have VCCIO = 2v5. My understanding is that LVDS inputs are supported here because they are powered off VCCPD=2v5.

Is this a documentation issue, or a Quartus error? I hope its the latter - the board is being built :-)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The clock input pins in the column I/O are actually powered by VCC_CLKIN:

    "VCCCLKIN powers the Column I/O bank dedicated clock input pins when configured as differential inputs. Clock input pins on the Column I/O banks

    use VCCIO when configured as single-ended inputs."

    The OCT calibration, however, leverages VCCIO, which is probably why you need VCCIO to be 2.5V in that bank. Do you have an OCT cal block in another 2.5V I/O bank? You could possibly use that without spinning your board.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks for the reply.

    I should have mentioned that it's a row IO that I'm using, so the clk inputs are from vccpd.

    The LVDS Rd does not seem to need cal. I'm simply applying a differentoal termination constraint (which the tool does not like). Is there some manual way I can do it, invoking a different bank's supply?

    I'm rather new to OCT - appreciate any help. Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    OCT = On Chip Termination. OCT Calibration blocks are instantiated by the user for calibrating on chip series and parallel termination. You are using differential termination, so you do not need to instantiate them.

    OCT blocks are still used for differential termination, and unfortunately OCT blocks always utilize VCCIO. So while you only need VCCPD for differential inputs, you still need VCCIO for differential inputs with termination.

    I know this is far from ideal, but perhaps you can turn off differential termination and place an external 100-ohm resistor across two vias on the differential pair?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Yeah, looks like we have add terminations on the pcb. For now, we can work round the problem by routing another clock internally as our PLL reference clock to that side of the chip but it is far from ideal.

    Unless I missed it (after many re-readings) the Altera documentation for stratix III does not point out this limitation, and it is far from obvious that VCCIO-powered OCT is required to invoke LVDS Rd.

    Thanks again for your help!