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Altera_Forum
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16 years ago

Using LVDS Rd, StratixIII 1v8 VCCIO

I get an error message when trying to apply a differential OCT (Rd) to an LVDS clock input which is on a bank with VCCIO=1v8 in a SIII part: Error: I/O bank 1C contains I/O pin p_rclk3 with Te...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for the reply.

I should have mentioned that it's a row IO that I'm using, so the clk inputs are from vccpd.

The LVDS Rd does not seem to need cal. I'm simply applying a differentoal termination constraint (which the tool does not like). Is there some manual way I can do it, invoking a different bank's supply?

I'm rather new to OCT - appreciate any help. Thanks!