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Honored Contributor
Honored ContributorUsing LVDS Rd, StratixIII 1v8 VCCIO
I get an error message when trying to apply a differential OCT (Rd) to an LVDS clock input which is on a bank with VCCIO=1v8 in a SIII part: Error: I/O bank 1C contains I/O pin p_rclk3 with Te...
Altera_ForumHonored Contributor
Honored ContributorYeah, looks like we have add terminations on the pcb. For now, we can work round the problem by routing another clock internally as our PLL reference clock to that side of the chip but it is far from ideal.
Unless I missed it (after many re-readings) the Altera documentation for stratix III does not point out this limitation, and it is far from obvious that VCCIO-powered OCT is required to invoke LVDS Rd. Thanks again for your help!
