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Altera_Forum
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16 years ago

Using LVDS Rd, StratixIII 1v8 VCCIO

I get an error message when trying to apply a differential OCT (Rd) to an LVDS clock input which is on a bank with VCCIO=1v8 in a SIII part: Error: I/O bank 1C contains I/O pin p_rclk3 with Te...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The clock input pins in the column I/O are actually powered by VCC_CLKIN:

"VCCCLKIN powers the Column I/O bank dedicated clock input pins when configured as differential inputs. Clock input pins on the Column I/O banks

use VCCIO when configured as single-ended inputs."

The OCT calibration, however, leverages VCCIO, which is probably why you need VCCIO to be 2.5V in that bank. Do you have an OCT cal block in another 2.5V I/O bank? You could possibly use that without spinning your board.