Using CRC detection with standalone FPGA

Question

Hello,

I'm planning a board with a standalone Stratis II FPGA. Since I have no external CPU on the board, I plan to use a EPCS device to configure the FPGA in AS mode.

I want to employ the run-time CRC detection feature of the Stratix II FPGA. However, when CRC fails the FPGA raises its CRC_ERROR pin and ... then what ?

Is there an elegant connection scheme to make the FPGA re-start its own configuration by AS from the EPCS if CRC_ERROR happened ? Or should I use a Max II with Flash memory instead of the EPCS ?

Thanks in advance

altera_forum · Answer

I think, that a re-configuration could be achived with simple logic, e.g. generating an nconfig pulse on a crcerror rising edge, if this solution would meet your requirements.

altera_forum · Answer

--- Quote Start ---

I think, that a re-configuration could be achived with simple logic, e.g. generating an nconfig pulse on a crcerror rising edge, if this solution would meet your requirements.

--- Quote End ---

Where do you recommend to place this logic ? In the FPGA itself ?

Usually nConfig goes from the configuration device to the FPGA. In what manner is it safe to connect another logic line to it ?

altera_forum · Answer

The usage of NCONFIG depends on the configuration scheme. For AS, as you requested it can trigger a reconfiguration, it has to be connected to an open drain driver. You'll find all necesssary detail in the Configuration Handbook or the respective FPGA documentation.

It may be possible to use internal logic also to connect CRC_ERROR to NCONFIG, although I imagined external logic primarly.

altera_forum · Answer

So you recommend an external open-drain logic, something like an open-drain buffer fed from '0' connected to nCONFIG, with CRC_ERROR serving as its enable with a pulldown ?

This way when CRC_ERROR is:

* 'Z' during FPGA configuration and initialization: pulldown makes driver disabled and nConfig isn't affected

* '0' when everything is normal during operation: same as above

* '1' when an error is detected: the buffer is enabled and transfers '0' to nCONFIG, which triggers FPGA reconfig, which in turn makes CRC_ERROR 'Z' again and closes the buffer.

Sounds reasonable ?

altera_forum · Answer

From the information given in the device handbook, a pull-down resistor at CRC_ERROR output should assure, that the output is high only in case of CRC error, so an open drain inverter is needed to connect it to NCONFIG, however you realize it.

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Using CRC detection with standalone FPGA

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