Using CRC detection with standalone FPGA

So you recommend an external open-drain logic, something like an open-drain buffer fed from '0' connected to nCONFIG, with CRC_ERROR serving as its enable with a pulldown ?

This way when CRC_ERROR is:

* 'Z' during FPGA configuration and initialization: pulldown makes driver disabled and nConfig isn't affected

* '0' when everything is normal during operation: same as above

* '1' when an error is detected: the buffer is enabled and transfers '0' to nCONFIG, which triggers FPGA reconfig, which in turn makes CRC_ERROR 'Z' again and closes the buffer.

Sounds reasonable ?