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Honored Contributorusing clock
Hi!
I'm a beginner with my DE2-115 and vhdl programations. I'm trying to do a simple logic: make a led blink. To do this, I'm working with clock. But, I'm with some problems, because the led doesn't blink! It just stays on and not blinking. This is the code I'm using: entity TESTE_CLOCK is port( clk:in bit; clkout:out bit); end TESTE_CLOCK; architecture behavior of TESTE_CLOCK is begin process(clk) variable cnt : integer range 0 to 50000000; begin if(clk'event and clk='1') then if(cnt=50000000)then cnt:=0; clkout<='0'; else cnt := cnt+1; clkout<='1'; end if; end if; end process; end behavior; Help me, please. tnx efsuzin3 Replies
Altera_ForumThat code makes clkout go low for a single clk period out of 50000000, so you can't see the 20ns-long blink (assuming a 50MHz clk)
You should change the inner if in this way: if(cnt=25000000)then cnt:=0; clkout<= NOT clkout; else cnt := cnt+1; end if;- Altera_Forum
Hi.
I've tryed to do the modifications, but with no success! Now, an error:Error (10309): VHDL Interface Declaration error in TESTE_CLOCK.vhd(13): interface object "clkout" of mode out cannot be read. Change object mode to buffer. can you help me again!? the code: entity TESTE_CLOCK is port( clk:in bit; clkout:out bit); end TESTE_CLOCK; architecture behavior of TESTE_CLOCK is begin process(clk) variable cnt : integer range 0 to 25000000; begin if(clk'event and clk='1') then if(cnt=25000000)then cnt:=0; clkout<= NOT clkout; else cnt := cnt+1; end if; end if; end process; end behavior; tnx - Altera_Forum
You can't directly control an output port from a process in VHDL 93. The idea is that for the hardware to be able to maintain a value on a signal outside of a clock edge, it needs to be able to read back the signal value, which is not possible with an output port.
You can either use a buffer signal to hold the value:
Or the other solution is to switch to VHDL 2008 which has removed that restriction on output ports and should run your code with no error. Any reason why you are using bit and not std_logic? std_logic is more standard, provides more features and (I think) needs to be used with the other IPs you can instantiate from Quartus.architecture behavior of TESTE_CLOCK is signal clkout_buffer : bit; begin clkout <= clkout_buffer; process(clk) clkout_buffer<= NOT clkout_buffer; end process; end behavior;
