using clock

You can't directly control an output port from a process in VHDL 93. The idea is that for the hardware to be able to maintain a value on a signal outside of a clock edge, it needs to be able to read back the signal value, which is not possible with an output port.

You can either use a buffer signal to hold the value:

architecture behavior of TESTE_CLOCK is
  signal clkout_buffer : bit;
begin
  clkout <= clkout_buffer;
  process(clk)
    clkout_buffer<= NOT clkout_buffer;
end process;
end behavior;

Or the other solution is to switch to VHDL 2008 which has removed that restriction on output ports and should run your code with no error.

Any reason why you are using bit and not std_logic? std_logic is more standard, provides more features and (I think) needs to be used with the other IPs you can instantiate from Quartus.