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Altera_Forum
Honored Contributor
14 years agousing clock
Hi! I'm a beginner with my DE2-115 and vhdl programations. I'm trying to do a simple logic: make a led blink. To do this, I'm working with clock. But, I'm with some problems, because the led doe...
Altera_Forum
Honored Contributor
14 years agoHi.
I've tryed to do the modifications, but with no success! Now, an error:Error (10309): VHDL Interface Declaration error in TESTE_CLOCK.vhd(13): interface object "clkout" of mode out cannot be read. Change object mode to buffer. can you help me again!? the code: entity TESTE_CLOCK is port( clk:in bit; clkout:out bit); end TESTE_CLOCK; architecture behavior of TESTE_CLOCK is begin process(clk) variable cnt : integer range 0 to 25000000; begin if(clk'event and clk='1') then if(cnt=25000000)then cnt:=0; clkout<= NOT clkout; else cnt := cnt+1; end if; end if; end process; end behavior; tnx