Altera_Forum
Honored Contributor
Honored ContributorUsing ALTPLL and ALTCLKCTRL (Clock Muxing)
I have 3 clocks that I want to select which clock to use for a certain part of my subsystem. 2 clocks are generated from the internal PLL and one is a external clock source.
Although the concept and code seems simple I keep on getting this error.: Error: inclk[1] port of Clock Control Block "altclkctrl0:inst2|altclkctrl0_altclkctrl_6df:altclkctrl0_altclkctrl_6df_component|clkctrl1" is driven by pll_device:inst|altpll:altpll_component|_clk1, but must be driven by a clock pin I tried to change around the ordering of my 3 clocks to the different pins of the ALTCLKCTRL and I still get a variation of the above warning. Anyone have any insight why I am having this problem?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_device is
port (
clk : in std_logic;
en : in std_logic;
clk_sel : in std_logic_vector(1 downto 0);
out_clk : out std_logic
);
end clock_device;
architecture behavior of clock_device is
component clock_pll
port
(
inclk0 : IN STD_LOGIC := '0';
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
);
end component;
component clock_switch
PORT
(
clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ena : IN STD_LOGIC := '1';
inclk0x : IN STD_LOGIC ;
inclk1x : IN STD_LOGIC ;
inclk2x : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
end component;
signal temp_c0,temp_c1 : std_logic;
begin
clockpll : clock_pll port map(
inclk0 => clk,
c1 => temp_c0,
c2 => temp_c1
);
clockswitch : clock_switch port map(
clkselect => clk_sel,
ena => en,
inclk0x => clk,
inclk1x => temp_c0,
inclk2x => temp_c1,
outclk => out_clk
);
end;
