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Honored Contributor
Honored ContributorUsing ALTPLL and ALTCLKCTRL (Clock Muxing)
I have 3 clocks that I want to select which clock to use for a certain part of my subsystem. 2 clocks are generated from the internal PLL and one is a external clock source. Although the conce...
Altera_ForumHonored Contributor
Honored ContributorIf you turn to the help on ALTCLKCTRL in Quartus II, you'll see there are some restrictions in connecting the input ports to different clock sources.
inclk[0] and inclk[1] need to be driven by clock pins and inclk[2] and inclk[3] need to be driven by a PLL clock output. So in your case, you need to instantiate a ALTCLKCTRL with four input ports: inclk0x, inclk1x, inclk2x and inclk3x. Connect inclk2x to temp_c0, inclk3x to temp_c1, inclk0x to clk. Connect inclk1x to '0'. Then you will pass the compilation :)
