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Altera_Forum
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14 years ago

Using ALTPLL and ALTCLKCTRL (Clock Muxing)

I have 3 clocks that I want to select which clock to use for a certain part of my subsystem. 2 clocks are generated from the internal PLL and one is a external clock source. Although the conce...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi jimbo,

Rysc is right in saying the solution is device dependent.

The solution I proposed is based on Cyclone III. For Cyclone III, we must generate ALTCLKCTRL megafunction with four clock inputs, if we want to implement the function supaflyfrank needs.

The way I connect these clocks to ALTCLKCTRL is just an example. The only restriction is that the two PLL clocks must go to inclk3x and inclk4x. The input clock pin can go to either inclk0x or inclk1x, with the remaining unused input connected to '0'. The interesting thing is, I find out, that you can't even connect the remaining unused input to '1' or input clock pin. The compilation would fail. You can only connect it to '0' to pass the compilation.

I think the help text on ATLCLKCTRL in Quartus II is not precise for every device. Because in your example, it is OK to just use three clock inputs of ATLCLKCTRL in Stratix. But definitely that won't work in Cyclone. Cyclone needs four clock inputs. Also, when we generate ATLCLKCTRL in Megawizard, we get sightly different options based on the target device.

So, supaflyfrank, the actual solution depends on the device you use.