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Altera_Forum
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14 years ago

Using ALTPLL and ALTCLKCTRL (Clock Muxing)

I have 3 clocks that I want to select which clock to use for a certain part of my subsystem. 2 clocks are generated from the internal PLL and one is a external clock source. Although the conce...
Altera_Forum's avatar
Altera_Forum
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14 years ago

@wdshen: This is true, however you do not have to connect the clocks up this way as the fitter will rearrange them for you. Changing the order of his clock connections will not fix his problem.

@Rysc: You can actually mux in the input clock with the PLL outputs. I didn't think you could either, but I tried it and it works.

@Supaflyfrank: The error you are getting seems to indicate that your input clock is not on a dedicated clock pin, which is a requirement for the ALTCLKCTRL. Did you assign pins in your design? The fitter will automatically put the input clock on a clock pin, which is why I'm asking.

I've attached at test design using Quartus II 11.1 in a Stratix IV device that shows that your code should work. Sorry, but I used Verilog. I'm not a VHDL guy.