Use FPGA to reclock audio I2S/ADAT/SPDIF signals

Hi,

Can you be more specific in the requirement here? Are you looking for a PLL reference design or any specific protocol?

Regards

There are several reference designs available for reference. Please check below links:

FPGA Wiki - Intel Communities

Intel® FPGA SDK for OpenCL Design Examples | Intel

Regards

Hello

I am looking for a solution to reclock:

- COAX SPDIF

- OPT SPDIF

- I2S (2 channels)

with extremely low jitter < 100-200fs.

An XMOS is generating above streams.

Plan is to use extremely precise clocks like Crystek or Accusilion 45.1584MHz & 49.152MHz (or multiple).

The "re-clocker" would take the COAX SPDIF and the OPT SPDIF and from above clock will reclock the signals by sending the clock back to the XMOS to get the data bits.

The "reclock" would take the I2S signals: CLK, LRCLK, DATA and reclock using above clocks.

There are tons of such boards on the market using Intel FPGA so I am quite sure this was already implemented. I do not want to re-invent the wheel

Thank you for any help!

Stephane.

Hi,

As I understand your requirement, I think you are looking for clock switching. Suggest you to please go clocking architecture of whichever device that is targeted. For example, following link talks about MAX 10 clock control block.

https://www.intel.com/content/www/us/en/docs/programmable/683047/21-1/global-clock-control-block.html

Also check the ALTCLKCTRL IP mentioned in the same document.

Regards

Hi,

As there are no further queries, I am setting this case to closure. However, it will still be open for the community members to comment.

Regards