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lelsteph's avatar
lelsteph
Icon for New Contributor rankNew Contributor
3 years ago

Use FPGA to reclock audio I2S/ADAT/SPDIF signals

Hello, I am completely new to FPGA / CPLD 😞 Any help or guidance will be really appreciate! I am looking for a way to reclock audio spdif/adat/i2s signal to remove jitter. It seems I can use som...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Can you be more specific in the requirement here? Are you looking for a PLL reference design or any specific protocol?


Regards