Use cyclone 10 GX transceiver as 1-bit ADC

I have a signal consisting of very fast sub-nanosecond pulses from the output of a comparator, and I am wondering if it's possible to use the multi-gigabit transceivers to sample and acquire the signal into the FPGA.

The pulses are derived from a random physical process, so they are completely asynchronous and have no intrinsic clock rate associated, and the signal is also not DC-balanced, therefore it also needs to be DC-coupled into the receiver inputs. For the time being I will assume we can successfully translate the comparator's logic levels to meet the receiver's differential and common mode voltage requirements.

My question is whether the transceivers can be set up to sample at a fixed frequency. I understand that CDR circuit can be operated in manual mode, and that there is a signal "locktoref". However it is not clear from the manuals whether my intended usage is sanctioned or if it produces well defined behavior. Can the receiver be continuously operated in locked to reference mode in order to sample a totally asynchronous signal? I would like to set up the PLL such that the receiver samples continuously at 10 GHz.

In essence, the receiver would be operating as a 1-bit ADC sampling the output signal from my comparator at a fixed frequency. I also wonder whether any metastability due to sampling near the edge of the pulse will be resolved once the deserialized signal is provided to the FPGA fabric, or if metastibility will cause any issues internal to the transceiver circuit.

I have already determined competitor A's transceiver can be operated in this mode, however the cyclone 10 GX has a better total # of transceivers in the price range we are targeting.

Thanks