Unused IO Banks

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If you dont mind could you have a quick look at my schematic and see if i have made any simple mistakes / missing any thing.

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You have 3.3V/800mA generated from 12V. If you really expect this supply to generate 800mA, it will dissipate P = (12V-3.3V) x 0.8 = 6.96W. It'll get way too hot. Use a switch-mode supply if you really expect to use this much power. A similar argument holds for the 5V supply.

I personally prefer to buffer or put series resistances in the path between the JTAG header and the JTAG pins on the FPGA. This provides some ESD protection ... that zap you hear, right before your board stops working.

nCONFIG needs a pull-up or pull-down. The low-to-high transition on that signal is what resets the FPGA. See this doc for more details:

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Put a series resistor in your DCLK path and on your oscillator output (to control ringing).

Where are all your decoupling capacitors? Make sure you have one per power pin for every device.

Check your crystal oscillator circuit. It seems a bit simple. I thought they normally had low valued capacitance near them to tune the oscillation.

Cheers,

Dave

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You have 3.3V/800mA generated from 12V. If you really expect this supply to generate 800mA, it will dissipate P = (12V-3.3V) x 0.8 = 6.96W. It'll get way too hot. Use a switch-mode supply if you really expect to use this much power. A similar argument holds for the 5V supply.

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I dont need 800ma i dont think the circuit will draw any where near that. im guessing only 100 or so?, i just like the lm1117 range of regulators + have tapes of them so decided to use it.

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I personally prefer to buffer or put series resistances in the path between the JTAG header and the JTAG pins on the FPGA. This provides some ESD protection ... that zap you hear, right before your board stops working.

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sounds good, what value resistor are you thinking some thing like a 1k?

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Check your crystal oscillator circuit. It seems a bit simple. I thought they normally had low valued capacitance near them to tune the oscillation.

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im not 100% sure on this i was just copying a simular schematic, ill look at the oscillator part data sheet and see if it needs this cap. :)

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nCONFIG needs a pull-up or pull-down. The low-to-high transition on that signal is what resets the FPGA. See this doc for more details:

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ah cool i shall add this.

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Where are all your decoupling capacitors? Make sure you have one per power pin for every device.

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all my decoupling caps are under the regulators top right of my schematic, i have 1 cap per pin for the 1.5core voltage and 2 caps, i think i just need 2 caps for my io banks as im only using 2 banks and these banks only use 3 pins and 2 of the pins are very close together. so i think i can get away with just 2 decoupling caps?

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Put a series resistor in your DCLK path and on your oscillator output (to control ringing).

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will do, what values should i be using?

thanks for all your feed back its VERY useful :) and ill make all your amendments.

ESD resistor: 100-Ohms is fine, 1K is Ok if thats what you have. You can always change them later if there is a problem with voltage drop.

Series resistors: something around 30-Ohms is good. Whatever you have close is good enough (eg., as big as 100-ohms would probably be ok - the key is to have them on the PCB ).

Cheers,

Dave

i can use any value, ill use your suggested values :)

OMG i completely forgot my data clock from the lpc to the fpga to clock the byte in haha, that would of sucked!!! lol