Unreliable D-FLOP

I've created a basic D-FLOP with a MAX3000 device. The FF clock input is driven by a debounced switch and the CPLD has an external reset chip and the FF reset input is mapped to the GCLR pin. When I push the button I should see a change of state on the FF output but sometimes it doesn't change. The CPLD is not clocked. I feel that I've missed something. My scope shows that the debounced input is good, supply rail is good, and GCLR is good.

module Controller

(switch,led,reset);

//INPUT PINS:

input switch;

input reset;

//OUTPUT PINS:

output led;

reg q1;

//Define FLIP FLOP Logic Here

always@(posedge switch or negedge reset) //SWITCH 1 D-flipflop

if (~reset)

begin

q1 <= 1'b0;

end

else begin

q1 <= ~q1;

end

initial q1 = 0;

assign led = ~q1; //Output pin to LED driver

endmodule